Illogical comparator output

Hi odedidush.

Did you run a testbench? You're using a process to compare. A process is like a black box with inputs and outputs. You have to place all inputs to the process in the sensitivity list:

process(ResetP, cmp_in_Rx, cmp_in_TX)

If you don't will be inferred latches. The process only activates if signals in sensitivuty list changes. If not, the output remains with its last value.

In practice, the synthetizer can't implement inferred latches, so your circuit keeps combinational, but simulation stills shows the inferred latch behavior. So, in this case, simultation behaves different from real fpga operation.