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Altera_Forum's avatar
Altera_Forum
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15 years ago

illegal/unconstrained/constrained clocks

What does it mean when the clock I use everywhere in the design, which happens to be the output of a PLL, is shown as "illegal" in the timing analyser clock status summary? And the raw clock input th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You need to constrain your input clock with a "create_clock command".

Then you need to constrain the PLL output clocks, using the "derive_pll_clocks" command.