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Altera_Forum
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10 years ago

Illegal connection from PLL to and gate

Hi there,

I have two plls in my quartus .bdf file. I have three clocks coming out from pll1 (c0,c1,c2). I have performed few anding operation given below:

cout4 = c0 and c1;

cout5= cout4 and c2

I have generated another clock co from pll2.

I want to perform another and operation between c0 from pll2 and cout5 from the previous pll1.

I am not able to do this, i have an error which is as follows

Error (176329): Illegal connection from Clock Control Block pll1:inst|altpll:altpll_component|pll1_altpll:auto_generated|wire_pll1_clk[0]~clkctrl to destination node inst4 -- destination node cannot be driven by global clock signals

Error (176329): Illegal connection from Clock Control Block pll1:inst|altpll:altpll_component|pll1_altpll:auto_generated|wire_pll1_clk[1]~clkctrl to destination node inst4 -- destination node cannot be driven by global clock signals

Error (176329): Illegal connection from Clock Control Block pll1:inst|altpll:altpll_component|pll1_altpll:auto_generated|wire_pll1_clk[2]~clkctrl to destination node inst4 -- destination node cannot be driven by global clock signals

Error (176329): Illegal connection from Clock Control Block pll2:inst2|altpll:altpll_component|pll2_altpll2:auto_generated|wire_pll1_clk[0]~clkctrl to destination node inst4 -- destination node cannot be driven by global clock signals

Can anybody help me find the solution ? Thank you in advance

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    You cannot do logical operations on PLL outputs. The wiring simply isn't there on the FPGA. PLL outputs are clocks. They can only be used as clocks, connected to clock inputs of other logic, or connected to clock output pins to drive clocks to other chips on the board.