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Altera_Forum
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10 years ago

Illegal connection from PLL to and gate

Hi there, I have two plls in my quartus .bdf file. I have three clocks coming out from pll1 (c0,c1,c2). I have performed few anding operation given below: cout4 = c0 and c1; cout5= cout4 and ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You cannot do logical operations on PLL outputs. The wiring simply isn't there on the FPGA. PLL outputs are clocks. They can only be used as clocks, connected to clock inputs of other logic, or connected to clock output pins to drive clocks to other chips on the board.