Ignored constraint

I need that constraint for the ASI IP.

If I remove the constraint I've the same result as now (20 path that have timing problems that will be resolved by that constraint for sure because they fail for less than 100ps in bad condition: the design still work now at ambient temperature, but I wanna be sure that all still work also later), moreover in the IP manual of the Altera Asi it's told to set theese constraints so I wanna them (also because if we release the FW and we'll have some problem and we'll resolve it putting the constraint, my chief ofc will kill me because it's an obvious thing to respect construnctor advise).

Normally PLL output names used in assignments do not end in "|c0" or "|c2". If the PLL node names in the first post are the names you have in the Assignment Editor without question marks by them, then I'm guessing those are names created by "keep" synthesis attributes in the IP's HDL, which might make them work in assignments.

However, the tsu and th assignments cannot be made between two clocks. The "th Requirement timing assignment" on-line help page and the similar tsu help page list all the valid combinations of "from" and "to" fields for the th and tsu assignments. None of those combinations is from a clock to a clock.

I agree with you Brad, but we don't agree with Altera asi_user_guide:

www.altera.com/literature/es/es_asi_100.pdf

Have a look at page A2 (constraint on Asi Receiver for non cyclone devices).

I report here for praticity:

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"These constraints apply to all device families (excluding Cyclone, but

including Cyclone II and Cyclone III device families) that are configured

to use a soft transceiver.

Define the following setup and hold relationship between the 135-MHz

clocks and the 337.5-MHz zero-degree clocks:

■ Setup—1.5 clocks (4.43 ns) from the 337.5-MHz zero degree clock to

the 135-MHz clock

■ Hold—zero clocks from the 337.5-MHz clock to the 135-MHz clock

Modify the following constraints and apply them to your design.

Alternatively, apply similar constraints to the clocks connected to the

rx_serial_clk and rx_clk135 signals on your ASI MegaCore

function.

Classic Timing Analyzer

Use the following constraints for the Classic Timing Analyzer:

set_instance_assignment -name SETUP_RELATIONSHIP "4.43 ns" -from "u_rx_pll|c0" -to "u_rx_pll|c2"

set_instance_assignment -name HOLD_RELATIONSHIP "0 ns" -from "u_rx_pll|c0" -to "u_rx_pll|c2"

Where c0 is a 337.5-MHz PLL output and c2 is the 135-MHz PLL output.

" [/end quote]

I cannot understood what he wanna do with this assignment because in my opinion 2 clock could have only a sort of shift between them.

Here it seems to me that they wanna that one of the 2 clock is in early respect the other, but the hold relationship equal to zero is too strange to understand to me.. (they wanna that one clock has less duty cycle? or is a sort of uncertainty.

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Something which sounds strange is the presence of the space character (in your initial post) between "inst" and "2" in both c0 and c2 cases. You may check this strange behaviour.

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It's only graphic here, there is no space in assignement.