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Altera_Forum's avatar
Altera_Forum
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17 years ago

Ignored constraint

I've set a Tsetup and a Thold on a PLL because it's the PLL of the Altera ASI IP that I use in my project.

I've not seen when and why (I've upgraded to Q8 Sp1 some days ago) this assignement is ignored and the message I've is for example this one:

" th Requirement 0 ns asi2rx2tx:inst58|asi_pll:inst1|sclk_pll_x50_4:inst2|c0 asi2rx2tx:inst58|asi_pll:inst1|sclk_pll_x50_4:inst2|c2

No element named dvb-t_mod_m was found in the netlist"

I cannot understand why it ignore it.

dvb-t_mod_m is the name of the top level of my project and the name of the directory.

Suggestions?

edit: I forgot to tell you that in Assignment Editor I've no error when I insert the constraint and after compilation they're ok (not with the "?" near).

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Are you using a device from the ArriaGX family? I've recently been told that the Classic Timing Analyzer has currently some bugs when working with the ArriaGX.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    Use the following constraints for the Classic Timing Analyzer:

    set_instance_assignment -name SETUP_RELATIONSHIP "4.43 ns" -from "u_rx_pll|c0" -to "u_rx_pll|c2"

    set_instance_assignment -name HOLD_RELATIONSHIP "0 ns" -from "u_rx_pll|c0" -to "u_rx_pll|c2"

    --- Quote End ---

    SETUP_RELATIONSHIP and HOLD_RELATIONSHIP are not the same Classic Timing Analyzer assignments as tsu and th. See the on-line help pages for all these assignments. The "Setup Relationship timing assignment" on-line help page and similar hold relationship page do list clock-to-clock as a valid form of those assignments (unlike the tsu and th assignments for I/O timing).