Sorry, I have to disagree with you that in order to simulate DDR4 in the past, I had to create my model from scratch. The tool supported including the model selectors for each I/O type and I simply had to modify the file slightly based on the wiki below to get it to work. Also, there was a switch to include the pin specific RLC values, not just the package ones. So not sure why you think it needed to be created custom. I've been using this method successfully since the DDR2 days.
https://community.intel.com/t5/FPGA-Wiki/Generating-and-Modifying-IBIS-files-for-Arria-10-EMIF/ta-p/736039
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