I would like to discuss my Timequest project . . .

Hi,

I just returned from a small training course on Timequest. Now, I implemented a *.sdc file for my project which cosits of a Cyclone III custom FPGA board connected to an ADC and a SRAM module.

I would like to ask if somebody would have a look over my project in order to tell me if everything is constrained the right way. I would upload the complete project and the important data sheet pages of the SRAM and ADC.

Although the Timequest course was very good I still have some questions after I started using it in a "real" project (e.g. how to constrain the clocks that go to the ADC and the SRAM and a SOPC user component or what Tsu and Th from the datasheet I have to use in output delay constrains (min or max)).

I hope somebody is interested in helping me this way.

Thanks,

Maik