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Altera_Forum
Honored Contributor
11 years agoyou should only assert start when clockdiv == 0 AND [some signal which indicates you have something to transmit and want to transmit it]. Else, the cycle pasted below will keep looping forever.
always @(posedge clk) begin case (state) 4'b0000: if (start) state <= 4'b0001; 4'b0001: if (serclock) state <= 4'b0010; // Start bit 4'b0010: if (serclock) state <= 4'b0011; // Bit 0 4'b0011: if (serclock) state <= 4'b0100; // Bit 1 4'b0100: if (serclock) state <= 4'b0101; // Bit 2 4'b0101: if (serclock) state <= 4'b0110; // Bit 3 4'b0110: if (serclock) state <= 4'b0111; // Bit 4 4'b0111: if (serclock) state <= 4'b1000; // Bit 5 4'b1000: if (serclock) state <= 4'b1001; // Bit 6 4'b1001: if (serclock) state <= 4'b1010; // Bit 7 4'b1010: if (serclock) state <= 4'b0000; // Stop bit default: state <= 4'b0000; // Undefined, skip to stop endcase end