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Please help me because I do not know how to start that.
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I can't help you if you don't specify what your design is supposed to do.
You should assert 'start' only when you really want your fpga to transmit something.
You can use the rising edge of an input signal (for example, what's the purpose of key_in signal? you could possibly use this).
Otherwise, if you may want your board to transmit back when it receives data: in this case you could assert start when rxstate=6'b100110
Advice:
That rxstate case statement is very cumbersome and somewhat unreadable. You could replace it with a simple increment of rxstate and a test on the two LSB
for the data[n] <= rxd assignement.
This is an example:
(please note I wrote this code by heart; I give you no assurance it works, not even it compiles without errors)
always @(posedge clk)
begin
if (rxstate >= 6'b100110)
begin
if (!rxd)
rxstate <= 6'b000000;
end
else
begin
rxstate <= rxstate + 6'b1;
if (rxstate[1:0] == 2'b10)
data[rxstate[5:2]-1] <= rxd;
end
end
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