I have created the Block Diagram file "Light Controller " and tried with Functional simulation. I have created the waveform and when i Run the Functional Simulation, I am getting the error and details are attached below. Requesting to solve this problem.

In the attached file, please refer the Project "light_control_new" and Waveform2.vwf file. Error report is attached below.

Determining the location of the ModelSim executable...

Using: /home/soorya/intelFPGA_lite/19.1/modelsim_ase/linuxaloem/

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options

Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off light_Control_new -c light_Control_new --vector_source="/media/soorya/New Volume/SK/Simulations/Altera Quartus Prime/Introdction_Tut_Practice/Waveform1.vwf" --testbench_file="/media/soorya/New Volume/SK/Simulations/Altera Quartus Prime/Introdction_Tut_Practice/simulation/qsim/Waveform1.vwf.vt"

Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Info: Copyright (C) 2019 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Sat Mar 28 15:50:06 2020Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off light_Control_new -c light_Control_new --vector_source="/media/soorya/New Volume/SK/Simulations/Altera Quartus Prime/Introdction_Tut_Practice/Waveform1.vwf" --testbench_file="/media/soorya/New Volume/SK/Simulations/Altera Quartus Prime/Introdction_Tut_Practice/simulation/qsim/Waveform1.vwf.vt"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Completed successfully.

Completed successfully.

**** Generating the functional simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/media/soorya/New Volume/SK/Simulations/Altera Quartus Prime/Introdction_Tut_Practice/simulation/qsim/" light_Control_new -c light_Control_new

Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Info: Copyright (C) 2019 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Sat Mar 28 15:50:08 2020Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/media/soorya/New Volume/SK/Simulations/Altera Quartus Prime/Introdction_Tut_Practice/simulation/qsim/" light_Control_new -c light_Control_newWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file light_Control_new.vo in folder "/media/soorya/New Volume/SK/Simulations/Altera Quartus Prime/Introdction_Tut_Practice/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 1139 megabytes Info: Processing ended: Sat Mar 28 15:50:09 2020 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01

Completed successfully.

**** Generating the ModelSim .do script ****

/media/soorya/New Volume/SK/Simulations/Altera Quartus Prime/Introdction_Tut_Practice/simulation/qsim/light_Control_new.do generated.

Completed successfully.

**** Running the ModelSim simulation ****

/home/soorya/intelFPGA_lite/19.1/modelsim_ase/linuxaloem//vsim -c -do light_Control_new.do

/home/soorya/intelFPGA_lite/19.1/modelsim_ase/linuxaloem//vish: error while loading shared libraries: libXext.so.6: cannot open shared object file: No such file or directory

Error.