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Honored Contributor
Honored Contributori create ram in maxII but it is error
I use max+plus II 10.2. i write the code but, the compiler says there is error.
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ram IS GENERIC ( bits: INTEGER := 8; --# of bits per word words: INTEGER := 16); --# of words in the memory PORT ( wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 TO 15; data_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0); data_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END ram; ARCHITECTURE ram OF ram IS TYPE vector_array IS ARRAY (0 TO 15) OF STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL memory: vector_array; BEGIN PROCESS (wr_ena,clk ) BEGIN IF (wr_ena='1') THEN IF (clk'EVENT AND clk='1') THEN memory(addr) <= data_in; END IF; END IF; END PROCESS; --data_out <= data_in; data_out <= memory(addr); END ram; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ram IS GENERIC ( bits: INTEGER := 8; --# of bits per word words: INTEGER := 16); --# of words in the memory PORT ( wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 TO 15; data_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0); data_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END ram; ARCHITECTURE ram OF ram IS TYPE vector_array IS ARRAY (0 TO 15) OF STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL memory: vector_array; BEGIN PROCESS (wr_ena,clk ) BEGIN IF (wr_ena='1') THEN IF (clk'EVENT AND clk='1') THEN memory(addr) <= data_in; END IF; END IF; END PROCESS; --data_out <= data_in; data_out <= memory(addr); END ram; But the compiler says: error line22: file unsupported feature error: condition statement in this region for signals not supported Is anybody know How to solve this problem ? :)
