I can't generate an Example Design of Displayport IP using Quartus Prime Pro 23.1.
I can't generate an Example Design of Displayport IP using Quartus Prime Pro 23.1.
Always prompt for an error.
Info: dp_0: Creating design example
Info: dp_0: Creating Core Qsys subsystem
Info: dp_0: Creating Rx Phy
Info: dp_0: Creating Tx Phy
Info: dp_0: Creating Clkrec
Warning: dp_0: clkrec_pll_s10.clkrec_pll_s10: The output frequencies are not exact when the PLL is in fractional mode. The tolerance is up to +/- 0.5Hz
Warning: dp_0: clkrec_pll_s10.clkrec_pll_s10: The output frequencies are not exact when the PLL is in fractional mode. The tolerance is up to +/- 0.5Hz
Warning: dp_0: clkrec_pll135_s10.clkrec_pll135_s10: The output frequencies are not exact when the PLL is in fractional mode. The tolerance is up to +/- 0.5Hz
Warning: dp_0: clkrec_pll135_s10.clkrec_pll135_s10: The output frequencies are not exact when the PLL is in fractional mode. The tolerance is up to +/- 0.5Hz
Info: dp_0: Creating Misc
Info: dp_0: Generating Reset Release Intel FPGA IP
Info: dp_0: Creating Software
Error: dp_0: starting the process ([wsl,
Error: dp_0: Debug from here: Error starting the process ([wsl,