I am having to re-assign the default pin, in Quartus II v 13.0sp1

I think I am there :

Connecting signals to assigned pins like IOC[3] appears to work in that, on compiling, the correct chip pin position are displayed on the .bdf diagram.

However connecting signals to assigned pins like IOC[3] are on a random basis ignored, new pins like IOC3 of arbitrary chip pin position sometimes being assigned, or the pin just being left disconnected, and shown in Ignored Assignments.

When there is a pin assigned, is possible to then use the Pin Planner to swap them back – unfortunately the diagram then displays the unwanted chip pin positions instead of the correct ones that it was displaying before.

So it is better to connect signals to un-assigned pins like IOC3; these will be left unassigned, but listed in the pin listing. Using Pin Planner one can then swap them with the correct bracketed pin such as IOC[3], which is then left unconnected. Thus one ends up with the signal connected to the correct chip pin position, and with this displayed correctly on the diagram.

I have not seen this strange behaviour even on earlier versions of the same circuit, a year or so ago.

Cheers,

Beau Webber