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Altera_Forum's avatar
Altera_Forum
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12 years ago

I am having to re-assign the default pin, in Quartus II v 13.0sp1

I have been using Quartus for many years, and have not seen this problem before - what am I doing wrong ? :

I have a top-level .bdf block diagram, that contains a .bdf with output that is linked directly to an output pin :

https://www.alteraforum.com/forum/attachment.php?attachmentid=7604

It shows IOC[3] linked to the correct FPGA pin, E3, as defined in the device assignment table.

When I compile, IOC[3] is left disconnected, a new pin IOC3 is created, and assigned to a FPGA pin that is not connected on the board.

If I use pin-swap, I can reassign IOC3 to FPGA pin E3.

I have also tried using pin name IOC3.

What is going on ? Am I omitting some necessary set-up information ?

The diagram is an existing one that already contains a number of input and output pins assigned in the same way, with no such problems.

cheers,

Dr. Beau Webber

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    OK, it seems that my pin assignments are being ignored :

    Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.

    The assignments I am using have been copied from MorphIO-II Rev1.2, which re-compiles and runs fine.

    Any ideas as to why they are being ignored ?

    cheers,

    Beau
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    I think I am there :

    Connecting signals to assigned pins like IOC[3] appears to work in that, on compiling, the correct chip pin position are displayed on the .bdf diagram.

    However connecting signals to assigned pins like IOC[3] are on a random basis ignored, new pins like IOC3 of arbitrary chip pin position sometimes being assigned, or the pin just being left disconnected, and shown in Ignored Assignments.

    When there is a pin assigned, is possible to then use the Pin Planner to swap them back – unfortunately the diagram then displays the unwanted chip pin positions instead of the correct ones that it was displaying before.

    So it is better to connect signals to un-assigned pins like IOC3; these will be left unassigned, but listed in the pin listing. Using Pin Planner one can then swap them with the correct bracketed pin such as IOC[3], which is then left unconnected. Thus one ends up with the signal connected to the correct chip pin position, and with this displayed correctly on the diagram.

    I have not seen this strange behaviour even on earlier versions of the same circuit, a year or so ago.

    Cheers,

    Beau Webber