Forum Discussion
RKath
New Contributor
7 years agoI tried Quartus 13.1 and this also did not work.
I did figure out a solution to my problem. The problem seemed to be related to global clock resource utilization around the PLLs. The clock input for all 3 of the ALTPLL_RECONFIG blocks (I believe this ends up feeding the pll_scanclk also) in my design was originally sourced from the same global clock net. I changed this so that each clock was generated locally by logic and forced the tool to prevent the use of global routing on the clocks feeding each reconfig block. This change allowed my design to compile and everything is working fine.