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ZC0001's avatar
ZC0001
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6 years ago

I am confused about the Equation 5 in the AN433

Hi,all. I am currently learning about FPGA interface constraints. Now I am confused about the Equation 5 in the AN 433: Constraining and Analyzing Source-Synchronous Interfaces.I don't know how to...
ZC0001's avatar
ZC0001
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6 years ago

Hi, IDeyn

Thanks for your reply.

I think i already understand why in the equation subtracting 'maximum delay of data' instead of tSU. Because the required time refers to the time when the data arrival at the FPGA output pin , not the time when the data reaches the external chip pin.

I don't know if I understand it correctly.

Best regards.

​ZC

IDeyn's avatar
IDeyn
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6 years ago

Hi ZC0001!

Hmmm, I also don't know if you understand correctly)

The main thing is that when you will write set_output_delay constraint, you will also take into account the path to the external chip.

So the idea is to constraint maximum skew between clock and data form the FPGA to external chip.

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Best regards,

Ivan