New Contributor
ContributorHi ZC0001!
First of all, I want to say that in my opinion Source Synchronous Interfaces better to understand using Intel FPGA free training video - Constraining Source Synchronous Interfaces (OCSS1000)
https://www.intel.com/content/www/us/en/programmable/support/training/course/ocss1000.html
As about your particular question, It should be understand, for example, like that.
Your case is FPGA-Centric Output Delay Constraints. In case of Edge-aligned transfer, the difference between latch and launch edge is zero,
so you only need to put into account clock arrival time - maximum delay of data, which is essentially the difference in delays from FPGA clock and data paths to external device.
Hope it helps.
You can ask for more detail if my explanation is not useful.
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Best regards,
Ivan
New ContributorHi, IDeyn
Thanks for your reply.
I think i already understand why in the equation subtracting 'maximum delay of data' instead of tSU. Because the required time refers to the time when the data arrival at the FPGA output pin , not the time when the data reaches the external chip pin.
I don't know if I understand it correctly.
Best regards.
ZC
ContributorHi ZC0001!
Hmmm, I also don't know if you understand correctly)
The main thing is that when you will write set_output_delay constraint, you will also take into account the path to the external chip.
So the idea is to constraint maximum skew between clock and data form the FPGA to external chip.
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Best regards,
Ivan
