How to write the 125 Mhz frequancy in a testbench vhdl language

--- Quote Start ---

thank you kaz

ok now i'm sure about the 8ns.

but the simulation dont provide result of 1s in the clock_s but it provide result of 0.5 s

is the problem in the value of the counter?!!

-------

thanks!

--- Quote End ---

your counter need to run from 0 to 125000000-1 freely

you set logic to zero or one when count = [0, 125,000,000/2 -1] respectively, or so depending on duty cycle.

process(rst,clk)
begin
if rst = '1' then
    count <= 0;
elsif rising_edge(clk) then
if count = 125000000-1 then 
    count <= 0;
else
   count <= count +1;
end if;
if count = 0 then
     clk_1s <= '0';
elsif count = 125000000/2 -1 then 
     clk_1s <= '1';
end if;
end if;
end process;

your simulation may get too long, you may scale it down by factor.

You also need clock edge