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Altera_Forum
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15 years ago

how to write test bench to see internal signals in ModelSIM-Altera

Hi, I've created a small microprocessor, with internal register, counter, ALU, ... and i want to see the internal value of some of them in the modelsim simulation (RTL and gate level). It was...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

In Verilog you should be able to access internal signals using UUU.sig_name notation.

A similar way should exist for VHDL