Forum Discussion
DNguy11
New Contributor
New ContributorHow to write a Verilog to implement -MULT(27x27) so that QPRO map the full functionality to 1 DSP?
Using QPRO it is possible to build an IP to implement -(X*Y) where X and Y are of 27 bit-width. However I find NO verilog writing style such that QPRO is able to map the full functionnality within 1 ...
KennyT_altera
Super Contributor
Super ContributorThat is correct, if you cannot find anything from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-qpp-design-recommendations-19-3.pdf?wapkw=12+recommended+hdl+coding+styles
Which means Qpro was not able to infer the DSP functionality base on your requirement. We can certainly make enhancement on this.
