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Altera_Forum
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15 years ago

How to use the $setup() system function in the testbench?

I want to use the $setup() and $hold() system function to check the setup time and hold time in the Verilog testbench,but there is a note show that " unexpected "$setup"" in the Modelsim.

could you help me?

thank you!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    ha ha!I have found the usage of the $setup(). 

    
`timescale 1 ns/ 1 ps
module diff_notifier(clk,data_A,data_B,data_out,reset);
input clk;
input reset;
input data_A;
input data_B;
output data_out;
specify
 $setup(data_A,posedge clk,1);
 $hold(posedge clk,data_A,0.1);
endspecify
endmodule
 
module LED_vlg_tst();
reg eachvec;
// test vector input registers
reg clk;
reg  data_A;
reg  data_B;
reg reset;
reg pha,phb;
// wires                                               
wire   data_out;
wire notifier;
integer TF;
integer i;
// assign statements (if any)                          
LED i1 (
// port map - connection between master ports and signals/registers   
 .clk(clk),
 .data_A(data_A),
 .data_B(data_B),
 .data_out(data_out),
 .reset(reset)
);
diff_notifier U1(clk,data_A,data_B,data_out,reset);
initial                                                
begin                                                  
clk=0;
TF=$fopen("DATABASE.txt");
$readmemb("WY.txt",pha);
$readmemb("KL.txt",phb);
for(i=0;i<8;i=i+1)
begin
# 5;
 data_A=pha;
 data_B=phb;
# 10;
 $fdisplay(TF,"%b",data_out);
# 5;
end
$fclose(TF);
                                      
$display("Running testbench");                       
end 
                                          
always# 10 clk=~clk;
                                                
endmodule