Forum Discussion
Altera_Forum
Honored Contributor
15 years agoha ha!I have found the usage of the $setup().
`timescale 1 ns/ 1 ps
module diff_notifier(clk,data_A,data_B,data_out,reset);
input clk;
input reset;
input data_A;
input data_B;
output data_out;
specify
$setup(data_A,posedge clk,1);
$hold(posedge clk,data_A,0.1);
endspecify
endmodule
module LED_vlg_tst();
reg eachvec;
// test vector input registers
reg clk;
reg data_A;
reg data_B;
reg reset;
reg pha,phb;
// wires
wire data_out;
wire notifier;
integer TF;
integer i;
// assign statements (if any)
LED i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.data_A(data_A),
.data_B(data_B),
.data_out(data_out),
.reset(reset)
);
diff_notifier U1(clk,data_A,data_B,data_out,reset);
initial
begin
clk=0;
TF=$fopen("DATABASE.txt");
$readmemb("WY.txt",pha);
$readmemb("KL.txt",phb);
for(i=0;i<8;i=i+1)
begin
# 5;
data_A=pha;
data_B=phb;
# 10;
$fdisplay(TF,"%b",data_out);
# 5;
end
$fclose(TF);
$display("Running testbench");
end
always# 10 clk=~clk;
endmodule