Altera_Forum
Honored Contributor
Honored Contributorhow to use testbench???
Here is my stupid question. I have a uart vhdl file. It has a testbench, also written in vhdl. How to use these testbench???
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Altera_ForumHonored Contributor
Honored ContributorCorrect - the testbench is what you select as the top level of your simulation
