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> 1. before I follow the chapter 5, do i have to fpga pin assignment & sof download?
yes you do.
but I think you already have assigned project with the development board.
if you have one, you don't have to assign the pins.
but yes,you need sof download.
> 2. in chapter 5, I don't understand customAddress variable.
> I can't find customAddress variable in verilog hdl source.
the customAddress means "base address" in SOPC builder.( see figure 14)
so you simply replace "0x00000000" into the address you got in SOPC builder.
all right, I will prepare next stage in next morning (morning for me).
see you.
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thank you for your kindness.
I followed your instruction, and I made sopc verilog source code like this.
============================================================
module SampleIP(iKEY, iCLK_50, oLEDG,
coe_out);
input [0:0] iKEY;
input iCLK_50;
output [7:0] oLEDG;
output [31:0] coe_out; ex1_SampleIP u_ex1_SampleIP
(
.clk_0 (iCLK_50),
.coe_out_from_the_mysampleip_0 (coe_out_from_the_mysampleip_0), .out_port_from_the_led_pio (oLEDG),
.reset_n (iKEY)
);
============================================================
Q> I have a pin map of development board as you said, and
I make top-level entity code for connection fpga board & sopc module
by using ex1_SampleIP_inst.v code.
What is the purpose of using LED?
And iCLK_50, iKEY, oLEDG are already assigned in pin map,
but, I don't know where ".coe_out_from_the_mySampleIP_0" is connected.
Do I have to connect from coe_out to LED for checking coe_out by using LED out?
Honored Contributor
