Honored ContributorHi.
I have source clk 250 MHz and PLL that generates 130 MHz from it. When I changed output PLL frequency to 150 MHz, my design has been faster, but TimeQuest "Report Clocks" reported about old frequency, 130 MHz. How can I update frequency? And what should I also constrain for PLL? Thank you.
Honored ContributorOK, I've found the solution:
1. Change PLL output frequency in Wizard. Remember High and Low parts of M, N, C counters. 2. Open your SDC file and find PLL VCO and output clocks definitions (create_generated_clock). 3. Edit VCO clock constraint: Fvco = Fin * M / N, so we should to edit "-multiply_by <M_value> -divide_by <N_value>", where each X_value = X_high + X_low, which we knew from step 1. 4. Edit output clock constraint: Fout = Fvco / C, so we should to edit "-divide_by <C_value>". C_value = C_high + C_low, of course. Maybe exists another method?
