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Altera_Forum
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10 years ago

How to update PLL frequency in TimeQuest

Hi. I have source clk 250 MHz and PLL that generates 130 MHz from it. When I changed output PLL frequency to 150 MHz, my design has been faster, but TimeQuest "Report Clocks" reported about old fr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

OK, I've found the solution:

1. Change PLL output frequency in Wizard. Remember High and Low parts of M, N, C counters.

2. Open your SDC file and find PLL VCO and output clocks definitions (create_generated_clock).

3. Edit VCO clock constraint: Fvco = Fin * M / N, so we should to edit "-multiply_by <M_value> -divide_by <N_value>", where each X_value = X_high + X_low, which we knew from step 1.

4. Edit output clock constraint: Fout = Fvco / C, so we should to edit "-divide_by <C_value>". C_value = C_high + C_low, of course.

Maybe exists another method?