How to undertand the STA.RTP file

Can you attached your actual report and the (or put in a snippet of it)

Negative setup and hold times are legal.

Normally setup time, is a requirement that data is stable N ns prior to the clock edge, and Hold time is a requirement that the data is still stable N ns after the clock edge.

Failure of hold time can cause the system to not work regardless of the clock rate. Failure of setup can cause the system to not work at the target frequency, but it will begin to work again at some lower frequency.

So most IC's have a small positive setup time requirement and a zero or very small positive hold requirement. for IO's.

IE 5ns setup 0 ns hold. However these datasheet values are based with temperature, voltage and process skews in consideration.

The actual register requirement will be a much smaller window (in the ps) but the clock and data path to the registers also have variance with them across the corners.

So as a starting so say the actual window of the register is 250 ps, to get the 5, 0 windows across corners, the design engineer (or tool in this case) may try to set it so that the "nominal" setup is 2.75 ns with a hold of -2.5 ns, expecting that window to drift across the corners.

If you have excessive clock path delay vs the data path, you may easily run into a condition where you have a negative setup and a postive hold. IE if the data path to the register is 500 ps, but the clock path to the register is 3.125 ns, you may end up with a -2.5 ns setup and a 2.75 ns hold requirement.

One of the reasons PLL's are often used in FPGA's is they can effectively zero out the internal clock delay.

Pete