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Honored Contributor
Honored ContributorHow to time constrain output pin connected to input pin on the same FPGA (design) ?
Hello, My design has output pin SYNC_OUT and input pin SYNC_IN, both synchronous, clocked by same clock. Pins connected externally on PCB with known max and min board delay. How do I cons...
Altera_ForumHonored Contributor
Honored ContributorThanks for the reply. It is not the FPGA path I want to constrain. It is the output path through board delay and then input path on the same FPGA.
Maybe better question would be how to constrain synchronous signal between two FPGAs. It is clear how ho constrain FPGA output path to say external memory with known Tsu, Th, but how to constrain FPGA to other FPGA where Tsu and Th are not known (derived by the tool from input / output path constraints). Any ideas?
