How to time constrain output pin connected to input pin on the same FPGA (design) ?

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Hello,

My design has output pin SYNC_OUT and input pin SYNC_IN, both synchronous, clocked by same clock. Pins connected externally on PCB with known max and min board delay.

How do I constrain these ports to meet timing from SYNC_OUT to SYNC_IN? I don't know any setup or hold times as both ports are on the same FPGA.

Thaks in advance

Vladimir

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You have three timing paths. input path, fpga path and output path.

You set constraints for input path, and for output path.

FPGA path (assuming it is between two registers) only needs clock definition and is checked by tool