How to tell timing closure is achieved? How to create real timing constraints?

Hi JPowe1!

First of all, you need to describe properly timing inside your FPGA. For that you need to tell TQ about your clock. You use PLL, and after derive_pll_clock TQ knows everything about timing paths inside FPGA except paths between FPGA regs and external devices. For external paths you need to create virtual clocks and probably exploit create_generated_clock command. You can of course use set_input and set_output_delay constraints, but your timing have a huge margin so most likely there is no need for this.

There are no typical values for input and output delays because they depend on speeds, type of interface, PCB board design, available I/O and logic and clock resourses and so on.

As about appnote, I think I could share that document wroty by David Hawkins, which was posted by him previously on alteraforum - https://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.pdf

Also for me the best work which explains Timing is Time_Quest User Guide by Ryan Scoville https://fpgawiki.intel.com/wiki/TimeQuest_User_Guide

But again, in your case timing constraints (except set_clock_groups or set_false_path) most likely would be an overkill.

Hope that helps.

Best regards,

Ivan