How to tell timing closure is achieved? How to create real timing constraints?

The SPI and Manchester clocks are lower speed than the FPGA clock and are asynchronous to the clocks in the external devices which generate timing for those devices and are at least as fast as the FPGA clock.

The external devices use the SPI clock and recovered clock from the data the FPGA sends to receive data when it's stable. The receiver will detect a SPI or Manchester clock edge no more than 2 FPGA clocks after the clock transition so that by the 3rd FPGA clock the data will be stable and the setup and hold times will be at least 1 FPGA clock.

While the FPGA and external clocks are asynchronous the data is synchronized through the mechanism described above.

Is there a way to describe this in an sdc file or is this something that can't be described or evaluated using TimeQuest?

Are there typical values for input and output delays to use for different families of FPGAs and/or clock speeds to put in the sdc?

Is there an apnote for a similar design I could use as a template?