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Altera_Forum
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18 years ago

how to synthesis SV file?

Hi there, I was trying to synthesis a SystemVerilog HDL module by using Altera Quartus II and found out that the HDL option does not contain SystemVerilog. Do anyone know how to synthesis SV...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Below is what I was told. I don't know the first Quartus version for which this applies.

Quartus automatically recognizes files with an .sv extension as SystemVerilog design files.

To process regular Verilog design files using SystemVerilog-2005, select SystemVerilog project wide or for an individual file.

Project wide: Assignments --> Settings --> Analysis & Synthesis Settings --> Verilog HDL Input --> Verilog version --> SystemVerilog-2005

Individual file: Assignments --> Settings --> Files, select the .v file, click Properties, set Type to Verilog HDL File and HDL version to SystemVerilog_2005.