How to suppress Fatal Modelsim error vsim-3807

This is because you have a VHDL syntax error, its not a design error. Quartus is quite relaxed in it's VHDL language conformance at times as it is trying to map things to real logic. But Modelsim must stick by the rules or some things just wont work properly. Using different types between the component and the entity is just illegal VHDL (and Im surprised Quartus allowed it). Why not just have unsigned/signed data types on the entity in the first place? std_logic_vector is meant to represent a bus, not arithmatic.

And then another option - why even bother using componenets at all? have you ever tried direct entity instantiation, which is been possible for nearly 25 years? it saves having to create all those components and will give you missmatch errors at the compile stage (usually occurs within seconds) rather than at the map stage (which can take several minutes).