Occasional Contributor
Super ContributorThese are not synthesis attributes. These are assignments you'd put in your .qsf file, either manually or using the Assignment Editor, targeting the specific part of the design where you want them applied.
Occasional ContributorThank you for answering.
I know about the .qsf and the Assignment editor. However, such assignments will only be present if I supply an entire project. I have developed SystemVerilog source code where I need specific modules to have specific settings depending on a set of parameters at the top of my code. It is not efficient for me to begin to instruct all my third parties who use my code to begin to setup numerous assignments based on their parameter selection within their own project when they import my code into their design.
Is there no way to specify a number of synthesis settings within my .sv code?
Super ContributorI don't understand. You have parameterizable IP that includes parameters that can change how Quartus compiles the design? The source files have to be a part of a project at some point.
I guess you could build a Tcl script that can be sourced by the .qsf file that can parse a design file and apply assignments as needed. Or you can use the revisions feature in Quartus to create a single project and then, depending on which design files you use, you create appropriate assignments for each project revision.
Maybe I'm not clear on what your end goal is.
Occasional ContributorI'm only trying to provide an ASCII .sv source code file for others to use in anyway they like, IE: integrate my function into their own project. I'm not trying to provide a complete Quartus project.
