Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThank you for answer, Galfonz!
Yes, I know - PLL is mixed part. But Altera has example - this one (https://www.altera.com/support/support-resources/design-examples/design-software/simulation/modelsim/exm-pll-simulation.html). Important - step of simulation should be 1 ps! And I have done it (did do? I'm not sure) successful for VHDL, not schematic (see details in first post). than i forgot it , because it was about month ago and this month i needed take a pause. so, will try remember. Any idea?