--- Quote Start ---
Thank you. I've figured it out.
Modelsim SE 6.5 supports sv features including class, assertion and randomization.
--- Quote End ---
Great!
Do you have any good references, suggestions on using these language features?
I've been using VHDL up until now, but the Altera verification suite uses SystemVerilog - but very poorly from what I have seen - they do not use classes, interfaces, etc. I think the limitation in their suite is likely due to the limitations in Modelsim Altera-Edition.
I purchased the two books;
"SystemVerilog for Design" 2nd Ed, Sutherland etc.
"SystemVerilog for Verification", 2nd Ed, Spear.
The latter discusses the features you are interested in.
I didn't look at UVM, OVM, VMM, and all the other TLAs (three-letter-acronyms) for test classes. Which one are you looking at - if any?
Cheers,
Dave
Honored Contributor
