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Altera_Forum
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14 years ago

How to simulate in SystemVerilog with Altera-Modelsim

Does the free version of Altera-Modelsim support system-verilog verification? I tried but as I changed the Simulation File Format to systemverilog, I can not launch Altera-Modelsim in Quartu...
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Altera_Forum
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14 years ago

Did you try starting Modelsim directly?

The Modelsim-Altera-Edition will allow you to process SystemVerilog, but it will not allow you to mix languages (VHDL + Verilog), so you have to generate things like SOPC system components in Verilog.

The full version of Modelsim and Mentor Graphics Questa supports mixed language design, SystemVerilog assertions, etc.

Cheers,

Dave