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ONors's avatar
ONors
Icon for New Contributor rankNew Contributor
6 years ago

How to simulate FFT IP Core in Modelsim.

I am trying to simulate the FFT IP Core in Modelsim - INTEL FPGA

STARTER EDITION 10.5b.

I have generated a simulation model from Qsys.

I have started Modelsim and navigated to the mentor sub directory and executed:

source msim_setup.tcl
dev_com
com

Some files are being compiled, but it fails with the following when trying to compile hyper_pipeline_interface.v.

# vlog -reportprogress 300 ./../../altera_fft_ii_161/sim/mentor/hyper_pipeline_interface.v -work fft_altera_fft_ii_161 
# ** Error: ./../../altera_fft_ii_161/sim/mentor/hyper_pipeline_interface.v(38): (vlog-2163) Macro `<protected> is undefined.
# ** Error: ./../../altera_fft_ii_161/sim/mentor/hyper_pipeline_interface.v(38): (vlog-2163) Macro `<protected> is undefined.
# ** Error: (vlog-13069) ./../../altera_fft_ii_161/sim/mentor/hyper_pipeline_interface.v(38): syntax error in protected region.
# 
# ** Error: ./../../altera_fft_ii_161/sim/mentor/hyper_pipeline_interface.v(38): (vlog-13205) Syntax error found in the scope following '<protected>'. Is there a missing '::'?
# End time: 12:41:36 on Mar 20,2019, Elapsed time: 0:00:00
# Errors: 5, Warnings: 0
# /opt/intelFPGA/16.1/modelsim_ase/linuxaloem/vlog failed.

How can I make the '<protected> macro defined or otherwise compile the FFT IP Core?

6 Replies

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    1. We have to use modelsim with respect to the Quartus version used to generate the fft design. please check the image attached and link. https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html
    2. Are you using Quartus 16.1 and Modelsim SE 10.5b? it should work fine.

    I have used Quartus 17.1 STD and Modelsim 10.5b under windows 10 environment. i was able to compile without any error.

    Attached the transcript .

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand

    • ONors's avatar
      ONors
      Icon for New Contributor rankNew Contributor
      6 years ago

      I was using this version of Quartus. Quartus Prime Design Software Version 16.1.1 Build 200 11/30/2016 SJ Standard Edition.

      I think the version of Modelsim is also from the 16.1*-version, but since Moelsim uses different version numbers than Quartus it is a bit difficult to tell.

      vsim -version

      Model Technology ModelSim ALTERA STARTER EDITION vsim 10.5b Simulator 2016.10 Oct 5 2016

      I went to the download page you linked to and saw a update to Quartus. So I updated to Quartus Prime Design Software Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition.

      I also uninstalled Modelsim and installed ModelSimSetup-16.1.0.196 from the same download page.

      vsim -version

      Model Technology ModelSim ALTERA STARTER EDITION vsim 10.5b Simulator 2016.10 Oct 5 2016

      Are these versions compatible?

      With the new versions and after regenerating the IP I still have the same error when compiling it in Modelsim.

      • AnandRaj_S_Intel's avatar
        AnandRaj_S_Intel
        Icon for Regular Contributor rankRegular Contributor
        6 years ago

        Hi,

        Yes, Tool versions are compatible.

        Can you please delete the db , incremental_db and libraries folders regenerate the qsys design and check.

        If possible please attache Modelsim transcript.

        Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

        Best Regards,

        Anand

  • Abe's avatar
    Abe
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Just tried the FFT IP with Quartus 16.1 and ModelSim 10.5b. Generated the FFT with default parameters , generated example design as well as testbench system using Qsys.

    Are you sure you have the license for the FFT IP core? This may be due to IP core licensing as well.

    When you generate the design and select the generate testbench/simulation files with Verilog option, a simulation folder will be created with the simulator specific scripts.

    When you generate the example design, Qsys will create an design example along with all necessary simulation scripts and data.

    Invoked ModelSim, changed directory to the generated FFT simulation/mentor or testbench/mentor directory .

    Sourced the msim_setup.tcl file in ModelSim command prompt - do msim_setup.tcl

    Compiled and Simulated design using the "ld_d" or "ld" command.

    ld_d - compile and simulation with debug options

    ld- compile and simulate

    Was able to simulate the design without any errors. Tried it for both generated design as well as generated example design. It works without any issues.

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi @ONors​ ,

    Have you solved the problem?

    Does my solution work for you or you have found solution.

    Kindly share the solution by posting in forum which will help other users too.

    Regards

    Anand