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Altera_Forum
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15 years ago

How to simulate a differential input driving a PLL?

I have a differential clock reference driving the pll inside my design. The problem is that I see that the reference clock input to the pll megafunction is single ended. This leads me to believe th...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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the code base that I had all had _p,_n pair signals.

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Depends on, what's the intended purpose of these signals. There are also special cases where pseudo-differential outputs are utilized. I was talking about the way, differential I/O would be used in reasonable HDL coding. Besides that, you have various other options, e.g. instantiating low-level primitives for differential I/Os and connecting them explicitely. You can find everything in the Quartus software and MegaFunction documentation, if you feel a need to use this stuff.