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Altera_Forum
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15 years ago

How to simulate a differential input driving a PLL?

I have a differential clock reference driving the pll inside my design. The problem is that I see that the reference clock input to the pll megafunction is single ended. This leads me to believe th...
Altera_Forum's avatar
Altera_Forum
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15 years ago

A differential in- or output can be represented by a single port bit in the HDL code. It becomes a differential signal by simply assigning a differential I/O standard in the pin planner or assignment editor.