Forum Discussion
Altera_Forum
Honored Contributor
17 years agoHow are you doing your design: schematic, VHDL, verilog?
Why do you need to extend one bit to sixteen bits? From what you've described, your vector is either all ones or all zeroes.How are you doing your design: schematic, VHDL, verilog?
Why do you need to extend one bit to sixteen bits? From what you've described, your vector is either all ones or all zeroes.