Altera_ForumHonored Contributor16 years agoHow to share settings among several QII projects I have one board layout that is used for several different FPGA designs. I want to share the parts of the settings that are the same among all the designs. The concept I want is an 'include' capabi...Show More
Altera_ForumHonored Contributor16 years agoI have common toplevel.v and .sdc files. How do you force the pin assignment in Verilog?
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: