How to set Timing Constraints (Tco, Tsu, Fast Output Register)

Question

Hi, I'm trying to include "Flash Altera IP University Program Core" into my project.  I read in this Altera tutorial (ftp:// ftp.altera.com/up/pub/Altera_Material/11.0/University_Program_IP_Cores/Memory/Flash_Memory_IP_Core.pdf) that  the timing constraints for the F L_¤ signals should be set as follows:
1. Fast Output Register &amp;#64258;ag should be turned ON
2. Tco requirement should be set to no more than 10ns, and
3. Tsu requirement should be set to no more than 10ns.  Could somebody tell me a step by step procedure to do these 3 setting?

altera_forum · Answer

for classic timing you enter tSU/tH/tCO directly for timequest you may find this thread useful   http://www.alteraforum.com/forum/showthread.php?p=125824#post125824

altera_forum · Answer

--- Quote Start ---

for classic timing you enter tSU/tH/tCO directly

for timequest you may find this thread useful

--- Quote End ---

Could you tell me a step by step procedure to do these 3 setting?

Forum Discussion

How to set Timing Constraints (Tco, Tsu, Fast Output Register)

2 Replies

Recent Discussions

Timing analysis - long combinational path

Docker image for Quartus Pro 26.1 missing ?

Error (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10

Agilex 5 – Critical HSSI Error in JESD204B Example Design

The quartus license works with version 25.0 but not with version 17.0