How to set Timing Constraint from CLR to Output?

Dear rbugalho,

I had tried both your suggestions before with no success :(

Timing report for "set_max_delay -from [get_ports read_n] -to [get_ports ack]" returns: "No paths were found"

For the second approach, I used:

create_clock -name dsp_clk -period 9.804
set_input_delay -clock { dsp_clk } -min 0 
set_input_delay -clock { dsp_clk } -max 0 
set_output_delay -clock { dsp_clk } -min 0 
set_output_delay -clock { dsp_clk } -max 0 

Timing report for "set_input_delay" returns: "No paths were found" (Which makes sense, as read_n is connected to the registers clock pin, not data pin as usual.)

Timing report for "set_output_delay" returns the clock pin to output port timing, which is not what I need. I'm looking for the clear to output timing.

My best approach so far is when using the following report:

report_timing -from_clock { dsp_clk } -recovery -npaths 10 -detail full_path -panel_name {read_n to ack_internal|q}

This shows the path from read_n port to ack_internal|q pin. But using "recovery" implements that I want to synchronize with the fpga_clk which is not what I'm after.

Is there some way of splitting timings into two "set_max_delay", one from read_n port to ack_internal|q and another for ack_internal|q to ack port? I tried some stuff like:

set_max_delay -from  -to  7
set_max_delay -from  -to  7
set_max_delay -from  -to  5
set_max_delay -from  -to  5

But all of them return: "No paths were found"!

Am I doing something wrong, or is this truly impossible to constrain?

Simon