Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

How to set Timing Constraint from CLR to Output?

Hi All, In my design I have a an output port, that must be driven low through an asynchronous clear within a certain limit of time. The post fitting Technology Map View looks like this: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Use set_max_delay should do it, I think

set_max_delay -from [get_ports read_n] -to [get_ports ack]

If not, you can try to define a virtual clock for that purpose and use set_input_delay and set_output_delay.