Forum Discussion
ZhiqiangLiang
Occasional Contributor
Occasional Contributorhow to set those parameters of clock crossing bridge?
Hi, My FPGA model is Cyclone 10 LP 10CL120YF484. on Platform Designer, NIOS frequency is 80MHz, and my IP is 160MHz. In NIOS C code, I would like to read/write registers of my IP. In my design, ...
I reviewed some diagrams on the website, and based on what I saw, option 2 is actually the correct setup. The diagrams clearly indicate that option 2 is the proper way to connect.
KennyT_altera
Super Contributor
Super ContributorWhen using an Avalon-MM Clock Crossing Bridge between an 80 MHz NIOS and a 160 MHz IP, connect the bridge’s master port to NIOS (the Avalon-MM master) and the slave port to the IP (the Avalon-MM slave). This ensures proper data flow and safe clock domain crossing. Reversing the connection may seem to work but can cause unreliable behavior. Always connect based on which side initiates the transactions.
