Forum Discussion
Altera_Forum
Honored Contributor
13 years agoWhy should q[1] period be not exactly 160ns? Provided the base clock is exactly 40ns, this is true.
I think you are missing a point about what TQ is supposed to do. TQ don't calculate design clocks: period and phase of clocks are indeed inputs you feed to TQ in order it can calculate the behavior of other signals, for example their relationship with the latching clock when they get to a register. Then if you use create_generated_clock or create_clock and declare a clock period different from the real one, TQ would use this one you specify, and all analysis results will be according to this value. From what you say, I believe you intend to evaluate q[1] signal jitter. In this case you only need to specify in TQ the 40ns base clock and analyse the q[1] timing.