How to remove timing check of synchronizer?

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I used synchronizer chain to pass signal from different clock domain. When I run a timing simulation, the synchronizers generate X status because of setup and hold violations.

Then I realized setup/hold time of the first stage of synchronizer should be set to zero.

I know I can modify the sdf file or use tcheck_set command to do this one by one.

The question is there are many synchronizer in my design, is there a better way to zero-ing synchronizer setup/hold time automatically?

P.S: I use Quartus II 8.0 and ModelSim SE

Thanks

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Hi,

if you want to switch off all the timing checks and you are using Verilog you can use the command line option +notimingchecks

Kind regards

GPK

You can use the Quartus x_on_violation_option logic option, but there is no way to automatically disable timing check for all synchronizers.

Note that top experts here would probably advise in most cases, to use functional simulation only. And use static timing verification instead of timing gate-level simulation.

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You can use the Quartus x_on_violation_option logic option, but there is no way to automatically disable timing check for all synchronizers.

Note that top experts here would probably advise in most cases, to use functional simulation only. And use static timing verification instead of timing gate-level simulation.

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I get it, Thanks