Altera_Forum
Honored Contributor
Honored ContributorHow to process this timing issue?
It seems the data path's delay is too big. Do you have any idea of decrease the data path delay?
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorAgreed, latch is not good for design, especially timing analyzer will have no information to analyze the path correctly. Design assistant will give warning on latches too
